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march 2011 ? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 fxlp34 ? single bit uni-di rectional translator fxlp34 single bit uni-directional translator features ? 1.0v to 3.6v v cc supply voltage ? converts any voltage (1.0v to 3.6v) to (1.0v to 3.6v) ? 4.6v tolerant inputs and outputs ? t pd : - 4ns typical for 3.0v to 3.6v v cc ? power-off high impedance inputs and outputs ? static drive (i oh /i ol ): - 2.6ma at 3.00v v cc ? uses proprietary quiet series? noise / emi reduction circuitry ? ultra-small micropak? leadless packages ? ultra-low dynamic power description the fxlp34 is a single translator with two separate supply voltages: v cc1 for input translation voltages and v cc for output translation voltages. the fxlp34 is part of fairchild?s ultra low power (ulp) series of products. this device operates with v cc values from 1.0v to 3.6v, and is intended for use in portable applications that require ultra lo w power consumption. the internal circuit is composed of a minimum of buffer stages, to enable ultra low dynamic power. the fxlp34 is uniquely designed for optimized power and speed, and is fabricat ed with an advanced cmos technology to achieve high-speed operation while maintaining low cmos power dissipation. ordering information part number top mark package packing method fxlp34p5x x34 5-lead sc70, eiaj sc-88a, 1.25mm wide 3000 units on tape & reel fxlp34l6x x3 6-lead micropak?, 1.00mm wide 5000 units on tape & reel fxlp34fhx x3 6-lead, micropak2, 1x1mm body, .35mm pitch 5000 units on tape & reel micropak? and quiet series? are trademarks of fairchild semiconductor corporation.
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 2 fxlp34 ? single bit uni-di rectional translator pin configuration figure 1. sc70 (top view) figure 2. micropak? (top through view) pin definitions pin # sc70 pin # micropak? name description 1 1 v cc1 input translation voltage 2 2 a input 3 3 gnd ground 4 4 y output 5 nc no connect 5 6 v cc output translation voltage truth table inputs outputs a y l l h h h = logic level high l = logic level low
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 3 fxlp34 ? single bit uni-di rectional translator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc , v cc1 supply voltage -0.5 +4.6 v v in dc input voltage -0.5 +4.6 v v out dc output voltage high or low state (1) -0.5 v cc +0.5v v v cc =0v -0.5 +4.6 i ik dc input diode current v in < 0 -50 ma i ok dc output diode current v out < 0v -50 ma v out > v cc +50 i oh /i ol dc output source/sink current 50 ma i cc or i gnd dc v cc or ground current per supply pin 100 ma t stg storage temperature range -65 150 c p d power dissipation at +85c sc70-6 180 mw micropak?-6 130 micropak2?-6 120 esd human body model, jedec:jesd22-a114 4000 v charge device model, jedec:jesd22-c101 2000 note: 1. i o absolute maximum rating must be observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc , v cc1 supply voltage 1.0 3.6 v v in input voltage 0 3.6 v v out output voltage high or low state 0 v cc v v cc =0v 0 3.6 i oh /i ol output current in i oh /i ol v cc =3.0 to 3.6v 2.6 ma v cc =2.3 to 2.7v 2.1 v cc =1.65 to 1.95v 1.5 v cc =1.40 to 1.60v 1.0 v cc =1.10 to 1.30v 0.5 v cc =1.0v 20 a t a operating temperature, free air -40 +85 c ? ja thermal resistance sc70-6 425 c/w micropak?-6 500 micropak2?-6 560 note: 2. unused inputs must be held high or low. they may not float.
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 4 fxlp34 ? single bit uni-di rectional translator electrical characteristics symbol parameter condition v cc (v) v cc1 (v) t a =+25c t a =-40 to +85c unit min. max. min. max. v ih high level input (v cc1 ) 1.0 to 3.6 1.0 0.65 x v cci 0.65 x v cci v 1.10 ? v cc1 ? 1.30 0.65 x v cci 0.65 x v cci 1.40 ? v cc1 ? 1.60 0.65 x v cci 0.65 x v cci 1.65 ? v cc1 ? 1.95 0.65 x v cci 0.65 x v cci 2.30 ? v cc1 ? 2.70 1.6 1.6 3.00 ? v cc1 ? 3.60 2.1 2.1 v il low level input 1.0 to 3.6 1.0 0.35 x v cci 0.35 x v cci v 1.10 ? v cc1 ? 1.30 0.35 x v cci 0.35 x v cci 1.40 ? v cc1 ? 1.60 0.35 x v cci 0.35 x v cci 1.65 ? v cc1 ? 1.95 0.35 x v cci 0.35 x v cci 2.30 ? v cc1 ? 2.70 0.7 0.7 3.00 ? v cc1 ? 3.60 0.9 0.9 v oh high level output (v cc ) i oh =-20a 1.0 1.0 to 3.6 v cc -0.1 v cc -0.1 v 1.10 ? v cc1 ? 1.30 v cc -0.1 v cc -0.1 1.40 ? v cc1 ? 1.60 v cc -0.1 v cc -0.1 1.65 ? v cc1 ? 1.95 v cc -0.1 v cc -0.1 2.30 ? v cc1 ? 2.70 v cc -0.1 v cc -0.1 3.00 ? v cc1 ? 3.60 v cc -0.1 v cc -0.1 i oh =-0.5ma 1.10 ? v cc1 ? 1.30 1.0 to 3.6 0.75 x v cc 0.70 x v cc i oh =-1.0ma 1.40 ? v cc1 ? 1.60 1.07 0.99 i oh =-1.5ma 1.65 ? v cc1 ? 1.95 1.24 1.22 i oh =-2.1ma 2.30 ? v cc1 ? 2.70 1.95 1.87 i oh =-2.6ma 3.00 ? v cc1 ? 3.60 2.61 2.55 v ol low level output i ol =20a 1.0 1.0 to 3.6 0.1 0.1 v 1.10 ? v cc1 ? 1.30 0.1 0.1 1.40 ? v cc1 ? 1.60 0.1 0.1 1.65 ? v cc1 ? 1.95 0.1 0.1 2.30 ? v cc1 ? 2.70 0.1 0.1 i ol =0.5ma 1.10 ? v cc1 ? 1.30 1.0 to 3.6 0.30 x v cc 0.30 x v cc i ol =1.0ma 1.40 ? v cc1 ? 1.60 0.31 0.37 i ol =1.5ma 1.65 ? v cc1 ?? 1.95 0.31 0.35 i ol =2.1ma 2.30 ? v cc1 ? 2.70 0.31 0.33 i ol =2.6ma 3.00 ? v cc1 ? 3.60 0.31 0.33 i in input leakage current 0 ?? v in ?? 3.60 1.0 to 3.6 0.1 1.0 a i off power off leakage current 0 ?? (v in , v o ) ?? 3.60 0 0 1.0 5.0 a i cc quiescent supply current v in =v cc or gnd 1.0 to 3.6 1.0 to 3.6 0.9 5.0 a continued on the following page?
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 5 fxlp34 ? single bit uni-di rectional translator ac electrical characteristics symbol parameter condition v cc1 (v) t a =+25c t a =-40 to +85c unit figure min. typ. max. min. max. t phl , t plh propagation delay output translation v cc (v)=1.0 c l =10pf, r l =1m ? 1.0 26.0 ns figure 3, figure 4 1.10 to 1.30 15.0 25.0 38.1 12.0 43.3 1.40 to 1.60 14.0 24.0 36.7 11.0 42.0 1.65 to 1.95 13.0 23.0 36.0 10.0 41.4 2.30 to 2.70 12.0 22.0 35.5 9.0 40.9 3.00 to 3.60 11.0 21.0 35.5 8.0 40.6 t phl , t plh propagation delay output translation v cc (v)=1.2 c l =10pf, r l =1m ? 1.0 18.0 ns figure 3, figure 4 1.10 to 1.30 8.0 15.0 23.2 6.0 41.0 1.40 to 1.60 7.5 14.0 21.7 5.5 39.1 1.65 to 1.95 7.0 13.0 20.9 5.0 32.3 2.30 to 2.70 6.5 12.0 20.4 4.5 29.6 3.00 to 3.60 6.0 12.0 20.2 4.0 29.4 t phl , t plh propagation delay output translation v cc (v)=1.5 c l =10pf, r l =1m ? 1.0 14.0 ns figure 3, figure 4 1.10 to 1.30 5.0 11.0 16.3 4.0 20.6 1.40 to 1.60 4.8 10.0 14.8 3.5 19.3 1.65 to 1.95 4.5 9.0 14.1 3.0 18.7 2.30 to 2.70 4.0 8.0 13.5 2.5 18.0 3.00 to 3.60 3.5 8.0 13.3 2.0 17.8 t phl , t plh propagation delay output translation v cc (v)=1.8 c l =10pf, r l =1m ? 1.0 13.0 ns figure 3, figure 4 1.10 to 1.30 4.0 9.0 13.5 3.0 17.5 1.40 to 1.60 3.5 8.0 12.0 2.5 16.3 1.65 to 1.95 3.0 7.0 11.3 2.0 15.6 2.30 to 2.70 2.5 6.0 10.7 1.5 15.0 3.00 to 3.60 2.5 6.0 10.5 1.0 14.7 t phl , t plh propagation delay output translation v cc (v)=2.5 c l =10pf, r l =1m ? 1.0 12.0 ns figure 3, figure 4 1.10 to 1.30 3.0 7.0 10.9 2.5 14.3 1.40 to 1.60 2.5 6.0 9.4 2.0 13.1 1.65 to 1.95 2.0 5.0 8.6 1.5 11.4 2.30 to 2.70 1.5 4.0 8.0 1.0 10.8 3.00 to 3.60 1.5 4.0 7.8 1.0 10.5 t phl , t plh propagation delay output translation v cc (v)=3.3 c l =10pf, r l =1m ? 1.0 11.0 ns figure 3, figure 4 1.10 to 1.30 3.0 6.0 10.1 2.0 13.8 1.40 to 1.60 2.5 5.0 8.2 1.5 10.5 1.65 to 1.95 2.0 4.0 7.4 1.0 9.9 2.30 to 2.70 1.0 3.0 6.8 1.0 9.2 3.00 to 3.60 1.0 3.0 6.6 1.0 9.0 continued on the following page?
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 6 fxlp34 ? single bit uni-di rectional translator ac electrical characteristics (continued) symbol parameter condition v cc1 (v) t a =+25c t a =-40 to +85c unit figure min. typ. max. min. max. t phl , t plh propagation delay output translation v cc (v)=1.0 c l =15pf, r l =1m ? 1.0 28.0 ns figure 3, figure 4 1.10 to 1.30 16.0 27.0 43.0 12.0 44.8 1.40 to 1.60 15.0 26.0 41.6 11.0 43.6 1.65 to 1.95 14.0 25.0 40.9 10.0 47.9 2.30 to 2.70 13.0 24.0 40.5 9.0 47.5 3.00 to 3.60 12.0 23.0 40.4 8.0 41.4 t phl , t plh propagation delay output translation v cc (v)=1.2 c l =15pf, r l =1m ? 1.0 19.0 ns figure 3, figure 4 1.10 to 1.30 9.0 16.0 24.6 8.0 43.1 1.40 to 1.60 8.5 15.0 23.1 7.5 42.2 1.65 to 1.95 8.0 14.0 22.4 7.0 31.4 2.30 to 2.70 7.5 13.0 21.8 6.5 30.7 3.00 to 3.60 7.0 13.0 21.6 6.0 30.5 t phl , t plh propagation delay output translation v cc (v)=1.5 c l =15pf, r l =1m ? 1.0 15.0 ns figure 3, figure 4 1.10 to 1.30 6.0 12.0 17.2 5.5 21.5 1.40 to 1.60 5.8 11.0 15.7 5.0 20.3 1.65 to 1.95 5.5 10.0 14.9 4.5 19.6 2.30 to 2.70 5.0 9.0 14.3 4.0 18.9 3.00 to 3.60 4.5 .0 14.2 3.5 18.7 t phl , t plh propagation delay output translation v cc (v)=1.8 c l =15pf, r l =1m ? 1.0 14.0 ns figure 3, figure 4 1.10 to 1.30 5.0 8.0 14.2 5.5 18.2 1.40 to 1.60 4.5 7.0 12.7 4.0 17.0 1.65 to 1.95 4.0 6.0 11.9 3.5 16.3 2.30 to 2.70 3.5 5.0 11.3 3.0 15.7 3.00 to 3.60 3.5 5.0 11.2 2.5 14.4 t phl , t plh propagation delay output translation v cc (v)=2.5 c l =15pf, r l =1m ? 1.0 12.0 ns figure 3, figure 4 1.10 to 1.30 4.0 7.0 11.3 3.5 14.9 1.40 to 1.60 3.5 6.0 9.8 3.0 13.6 1.65 to 1.95 3.0 5.0 9.1 2.5 12.0 2.30 to 2.70 2.5 4.0 8.5 2.0 11.3 3.00 to 3.60 2.5 4.0 8.3 2.0 11.1 t phl , t plh propagation delay output translation v cc (v)=3.3 c l =15pf, r l =1m ? 1.0 11.0 ns figure 3, figure 4 1.10 to 1.30 3.0 6.0 10.5 2.0 14.2 1.40 to 1.60 2.5 5.0 8.6 1.5 11.0 1.65 to 1.95 2.0 4.0 7.8 1.0 10.3 2.30 to 2.70 1.5 3.0 7.2 1.0 9.7 3.00 to 3.60 1.5 3.0 7.0 1.0 9.4 continued on the following page?
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 7 fxlp34 ? single bit uni-di rectional translator ac electrical characteristics (continued) symbol parameter condition v cc1 (v) t a =+25c t a =-40 to +85c unit figure min. typ. max. min. max. t phl , t plh propagation delay output translation v cc (v)=1.0 c l =30pf, r l =1m ? 1.0 34.0 ns figure 3, figure 4 1.10 to 1.30 19.0 32.0 48.6 15.0 55.5 1.40 to 1.60 18.0 31.0 47.1 14.0 52.3 1.65 to 1.95 17.0 30.0 46.4 13.0 50.6 2.30 to 2.70 16.0 29.0 45.9 12.0 49.2 3.00 to 3.60 15.0 28.0 45.8 10.0 49.1 t phl , t plh propagation delay output translation v cc (v)=1.2 c l =30pf, r l =1m ? 1.0 22.0 ns figure 3, figure 4 1.10 to 1.30 11.0 19.0 29.0 10.0 46.5 1.40 to 1.60 10.0 18.0 27.5 9.0 42.6 1.65 to 1.95 9.0 17.0 26.7 8.0 36.7 2.30 to 2.70 8.5 16.0 26.1 7.0 36.0 3.00 to 3.60 8.0 16.0 26.0 6.0 35.9 t phl , t plh propagation delay output translation v cc (v)=1.5 c l =30pf, r l =1m ? 1.0 16.0 ns figure 3, figure 4 1.10 to 1.30 6.0 13.0 19.8 5.5 25.3 1.40 to 1.60 5.8 12.0 18.3 5.0 23.0 1.65 to 1.95 5.5 11.0 17.6 4.5 22.4 2.30 to 2.70 5.0 10.0 17.0 4.0 21.7 3.00 to 3.60 4.5 9.0 16.8 3.5 21.5 t phl , t plh propagation delay output translation v cc (v)=1.8 c l =30pf, r l =1m ? 1.0 15.0 ns figure 3, figure 4 1.10 to 1.30 5.0 11.0 16.2 5.5 20.4 1.40 to 1.60 4.5 10.0 14.7 4.0 19.2 1.65 to 1.95 4.0 9.0 13.9 3.5 18.5 2.30 to 2.70 3.5 8.0 13.3 3.0 17.9 3.00 to 3.60 3.5 8.0 13.1 2.5 17.6 t phl , t plh propagation delay output translation v cc (v)=2.5 c l =30pf, r l =1m ? 1.0 13.0 ns figure 3, figure 4 1.10 to 1.30 4.0 8.0 12.7 3.5 15.9 1.40 to 1.60 3.5 7.0 11.2 3.0 14.3 1.65 to 1.95 3.0 6.0 10.5 2.5 13.6 2.30 to 2.70 2.5 5.0 9.9 2.0 12.8 3.00 to 3.60 2.5 5.0 9.7 2.0 12.5 t phl , t plh propagation delay output translation v cc (v)=3.3 c l =30pf, r l =1m ? 1.0 12.0 ns figure 3, figure 4 1.10 to 1.30 3.0 8.0 11.7 2.0 15.0 1.40 to 1.60 2.5 7.0 9.8 1.5 12.2 1.65 to 1.95 2.0 6.0 8.9 1.0 11.5 2.30 to 2.70 1.5 5.0 8.3 1.0 10.7 3.00 to 3.60 1.5 5.0 8.1 1.0 10.4 capacitance symbol parameter conditions v cc / v cc1 (v) t a =+25c units typical c in input capacitance 2 pf c i/o input/output capacitance 4 pf c pd power dissipation capacitance v i =0v or v cc1 , f=10mhz, v cc / v cc1 =3.6v 1.0 to 3.60 8 pf
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 8 fxlp34 ? single bit uni-di rectional translator translator power-up sequence recommendations to ensure that the syst em does not experience unnecessary i cc current draw, bus contention, or oscillations during power-up; adhere to the following guidelines. this device is des igned with the output pin(s) supplied by v cc and the input pin(s) supplied by v cc1 . the first recommendation is to begin by powering up the input side of the device with v cc1 . the input pin(s) should be ramped with or ahead of v cc1 or held low. this guards against bus cont entions and oscillations as all inputs and the input v cc1 are powered at the same time. the output v cc can then be powered to the target voltage level to which the device will translate. the output pin(s) then translate to logic levels dictated by the output v cc levels. upon completion of these steps, the device can be configured for the desired operation. following these steps helps prevent possibl e damage to the translator device as well as other system components. ac loadings and waveforms figure 3. ac test circuit figure 4. waveform for inverting and non-inverting functions table 1. ac load table symbol v cc 3.3v 0.3v 2.5v 0.2v 1.8v 0.15v 1.5v 0.10v 1.2v 0.10v 1.0v v mi 1.5v v cc1 /2 v cc1 /2 v cc1 /2 v cc1 /2 v cc1 /2 v mo 1.5v v cc /2 v cc /2 v cc /2 v c c/2 v cc /2
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 9 fxlp34 ? single bit uni-di rectional translator physical dimensions figure 5. 5-lead, sc70, eiaj sc-88a, 1.25mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf . package designator tape section cavity number cavity status cover type status p5x leader (start end) 125 (typical) empty sealed carrier 3000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 10 fxlp34 ? single bit uni-di rectional translator physical dimensions 2. dimensions are in millimeters 1. conforms to jedec st andard m0-252 va riation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 terminal 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout. figure 6. 6-lead, micropak?, 1.0mm wide package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l6x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 11 fxlp34 ? single bit uni-di rectional translator physical dimensions 1.00 b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994 notes: a. complies to jedec mo-252 standard 0.05 c a b 0.55max 0.05 c c 0.35 0.09 0.19 123 0.35 0.25 5x 6x detail a 0.60 (0.08) 4x (0.05) 6x 0.40 0.30 0.075x45 chamfer 5x 0.40 0.35 1x 0.45 6x 0.19 top view bottom view 0.66 0.10 cba .05 c 0.89 pin 1 0.05 c 2x 2x 1.00 d. landpattern recommendation is based on fsc e. drawing filename and revision: mgf06arev3 0.52 0.73 0.57 0.20 6x 1x 5x recommended land pattern for space constrained pcb detail a pin 1 lead scale: 2x alternative land pattern for universal application design. 0.90 min 250um 65 4 0.35 (0.08) 4x side view figure 7. 6-lead, micropak2?, 1x1mm body, .35mm pitch package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/packaging/micropak2_6l_tr.pdf . package designator tape section cavity number cavity status cover type status fhx leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2006 fairchild semiconductor corporation www.fairchildsemi.com fxlp34 ? rev. 1.0.4 12 fxlp34 ? single bit uni-di rectional translator

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